Directed Electronics 3200HS Informações Técnicas Página 9

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SCI to SPI Peripheral Communication in V850ES Microcontrollers
When the CSI peripheral is not used, the SCK, SO, and SI I/O pins can be used as port pins. The CSI
units are configured using mode registers, control registers, configuration registers, and dedicated
hardware logic.
Table 1. Description of Registers
Register Type Register Name Symbol Functional Description
CSI Mode (8-bit) CSIM0n Specifies CSI operation
Control
Clock Selection CSICn Controls CSI serial transfer operation
Shift (8-, 16-bit) SIO0n/SIO0nL Converts parallel data to serial data
Receive Buffer (8-, 16-bit) SIRBn/SIRBnL Buffer register for receive data
Transmit Buffer (8-, 16-bit) SOTBn/SOTBnL Buffer register for transmit data
Configuration
Initial Transmit Buffer SOTBFn/SOTBFnL Stores initial data in continuous transfer mode
Clock Select Logic Selects the serial clock to be used
Serial Clock Counter Controls the serial clock to the Shift Register
Configuration
Hardware Logic
Interrupt Controller Controls interrupt request timing
The CSI Mode register configures the CSI unit for:
Enabled or disabled operation
Receive-only mode or transmit and receive mode
8- or 16-bit data length
Most significant bit (MSB) or least significant bit (LSB) first
Single or continuous transfer
Clock selection and CSI transfer operation depends on:
Whether a positive or negative edge of the clock is used for the data capture strobe (clock polarity)
Whether the first edge of clock is used for the ata capture or data drive strobe (clock phase)
For example, the timing diagram shown in Figure 2 illustrates a positive-edge data capture, with the first
edge of clock used for data capture and the trailing edge for data drive strobe. See type 4 in Figure 3.
It is important to note that the master unit controls the serial clock. If the first edge of the serial clock is
used for the data capture strobe, the slave unit must be ready with data (driving data) before the first edge
of the serial clock. Typically, in this case, the Chip Select signal is used to indicate the start of
transmission from the master unit.
3
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