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CSI to SPI Peripheral Communication in V850ES Microcontrollers

Most NEC Electronics MCUs incorporate one or more channels of CSI peripheral, for easy

interconnection of devices. This type of interface can also be configured to connect to other devices

supporting a 3-wire clocked serial interface.

In 3-wire serial I/O communication, data is transmitted or received in eight-bit units; some NEC

Electronics MCUs allow transmission in 16-bit units. Each bit of data is transmitted or received in

synchronization with the serial clock. One side of the communication controls the clock line, so this is a

master-slave configuration, typically with one master and one slave.

If only one slave device drives data back to the master, multiple slaves receiving data can be supported

without additional hardware. If multiple slaves need to drive data back to the master, additional chip

select lines and logic must be implemented.

In communication situations where data is sent in both directions, transmission time can be shortened

using CSI, since transmit and receive transfers can be executed simultaneously.

2.1 NEC Electronics CSI Communication

The clocked serial interface (CSI) peripheral implemented for the V850ES devices typically offer the

following features. Many devices offer multiple channels of CSI units. The following is a list of features

offered for the 32-bit µPD70F3318 MCU, a device in the V850ES/KJ1+ product line. Most NEC

Electronics 32-bit MCUs offer similar CSI features.

• Maximum transfer speed: up to 5 Mbps

• Selectable master and slave modes

• Transmission data length: 8 or 16 bits

• MSB/LSB-first selection option for data transfer

• Multiple clock signals

• 3-wire type (three channels of CSI as implemented for the µPD70F3318Y MCU)

− SO0n: serial transfer data output, where n = 0–2

− SI0n: serial receive data input, where n = 0–2

− SCK0n_B: serial clock, where n = 0–2

• Transmission/reception completion interrupt

• Selectable transmit and receive mode or receive-only mode

• Two transmission buffer registers and two reception buffer registers

• Selectable single transfer mode or continuous transfer mode

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