
SCI to SPI Peripheral Communication in V850ES Microcontrollers
Figure 8. MCU Connections to DS1722 Temperature Sensor
CE
SDI
SCLK
SDO
DS1722
SERMODE
µC
The polarity of the serial clock depends on its state when CE is asserted. Assuming SCLK is low when
CE goes high, the idle state of SCLK is low, which is equivalent to CPOL=0. If SCLK is high when CE
goes high, the idle state of SCLK is high, which is equivalent to CPOL=1.
For compatibility with the MAX6627, we will assume SCLK is low when idle (CPOL=0), and the first
edge of SCLK will be a rising edge. The interface to master unit uses the first edge of the serial clock as
the data drive strobe (when driving data to the master) and the trailing edge of serial clock as the data
capture strobe (when accepting data from the master). For an SPI controller, this would require CPHA=1,
which is equivalent to an NEC Electronics CSI type 3 interface.
NEC Electronics CSI clocking type CKPn = 1 DAPn = 0 Type 3 interface
SPI clocking method CPOL = 0 CPHA = 1
After CE is activated, the DS1722 sensor expects the master to transmit an address by sending eight bits
of data to SDI; during these eight bits, the SDO output will be in the high-impedance state, and the
DS1722 will clock in eight bits of address on the trailing edges of SCLK. Depending on the address, the
DS1722 will then drive SDO, ignoring further input on SDI (read operation from DS1722), or will
continue to read data on SDI and keep SDO in the high-impedance state (write operation to DS1722).
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